From d656d97818fdf5a0e92b451410decaa08529f1e9 Mon Sep 17 00:00:00 2001
From: JoYo <>
Date: Wed, 26 Jan 2022 14:37:24 -0500
Subject: [PATCH] the rest of rizin architectures

---
 subdisassem/rizin_wrapper.py | 349 +++++++++++++++++++++++++++++++++--
 subdisassem/scripts.py       |  83 +++++++++
 2 files changed, 415 insertions(+), 17 deletions(-)

diff --git a/subdisassem/rizin_wrapper.py b/subdisassem/rizin_wrapper.py
index 69302d6..d660d64 100644
--- a/subdisassem/rizin_wrapper.py
+++ b/subdisassem/rizin_wrapper.py
@@ -124,87 +124,362 @@ class _RizinBase:
 
 class _6502_8(_RizinBase):
     arch_cmds = ["e asm.arch=6502", "e asm.bits=8"]
-    name = "6502/NES/C64/Tamagotchi/T-1000 CPU"
 
 
 class _6502_16(_RizinBase):
     arch_cmds = ["e asm.arch=6502", "e asm.bits=16"]
-    name = "6502/NES/C64/Tamagotchi/T-1000 CPU"
 
 
 class _8051(_RizinBase):
     arch_cmds = ["e asm.arch=8051", "e asm.bits=8"]
-    name = "8051 Intel CPU"
 
 
 class amd29k(_RizinBase):
     arch_cmds = ["e asm.arch=amd29k", "e asm.bits=32"]
-    name = "AMD 29k RISC CPU"
 
 
 class arc_16(_RizinBase):
     arch_cmds = ["e asm.arch=arc", "e asm.bits=16"]
-    name = "Argonaut RISC Core"
 
 
 class arc_32(_RizinBase):
     arch_cmds = ["e asm.arch=arc", "e asm.bits=32"]
-    name = "Argonaut RISC Core"
 
 
 class arm_as_16(_RizinBase):
     arch_cmds = ["e asm.arch=arm.as", "e asm.bits=16"]
-    name = "as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)"
 
 
 class arm_as_32(_RizinBase):
     arch_cmds = ["e asm.arch=arm.as", "e asm.bits=32"]
-    name = "as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)"
 
 
 class arm_as_64(_RizinBase):
     arch_cmds = ["e asm.arch=arm.as", "e asm.bits=64"]
-    name = "as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)"
 
 
 class arm_16(_RizinBase):
     arch_cmds = ["e asm.arch=arm", "e asm.bits=16"]
-    name = "Capstone ARM disassembler"
 
 
 class arm_32(_RizinBase):
     arch_cmds = ["e asm.arch=arm", "e asm.bits=32"]
-    name = "Capstone ARM disassembler"
 
 
 class arm_64(_RizinBase):
     arch_cmds = ["e asm.arch=arm", "e asm.bits=64"]
-    name = "Capstone ARM disassembler"
 
 
 class arm_gnu_16(_RizinBase):
     arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=16"]
-    name = "Acorn RISC Machine CPU"
 
 
 class arm_gnu_32(_RizinBase):
     arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=32"]
-    name = "Acorn RISC Machine CPU"
 
 
 class arm_gnu_64(_RizinBase):
     arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=64"]
-    name = "Acorn RISC Machine CPU"
 
 
 class arm_wine_16(_RizinBase):
     arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=16"]
-    name = "WineDBG's ARM disassembler"
 
 
 class arm_wine_32(_RizinBase):
     arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=32"]
-    name = "WineDBG's ARM disassembler"
+
+
+class avr_8(_RizinBase):
+    arch_cmds = ["e asm.arch=avr", "e asm.bits=8"]
+
+
+class avr_16(_RizinBase):
+    arch_cmds = ["e asm.arch=avr", "e asm.bits=16"]
+
+
+class bf_16(_RizinBase):
+    arch_cmds = ["e asm.arch=bf", "e asm.bits=16"]
+
+
+class bf_32(_RizinBase):
+    arch_cmds = ["e asm.arch=bf", "e asm.bits=32"]
+
+
+class bf_64(_RizinBase):
+    arch_cmds = ["e asm.arch=bf", "e asm.bits=64"]
+
+
+class bf_64(_RizinBase):
+    arch_cmds = ["e asm.arch=bf", "e asm.bits=64"]
+
+
+class chip8(_RizinBase):
+    arch_cmds = ["e asm.arch=chip8", "e asm.bits=32"]
+
+
+class cr_16(_RizinBase):
+    arch_cmds = ["e asm.arch=cr16", "e asm.bits=16"]
+
+
+class cris(_RizinBase):
+    arch_cmds = ["e asm.arch=cris", "e asm.bits=32"]
+
+
+class dalvik_32(_RizinBase):
+    arch_cmds = ["e asm.arch=dalvik", "e asm.bits=32"]
+
+
+class dalvik_64(_RizinBase):
+    arch_cmds = ["e asm.arch=dalvik", "e asm.bits=64"]
+
+
+class dcpu16(_RizinBase):
+    arch_cmds = ["e asm.arch=dcpu16", "e asm.bits=16"]
+
+
+class ebc_32(_RizinBase):
+    arch_cmds = ["e asm.arch=ebc", "e asm.bits=32"]
+
+
+class ebc_64(_RizinBase):
+    arch_cmds = ["e asm.arch=ebc", "e asm.bits=64"]
+
+
+class gb(_RizinBase):
+    arch_cmds = ["e asm.arch=gb", "e asm.bits=16"]
+
+
+class h8300(_RizinBase):
+    arch_cmds = ["e asm.arch=h8300", "e asm.bits=16"]
+
+
+class hexagon(_RizinBase):
+    arch_cmds = ["e asm.arch=hexagon", "e asm.bits=32"]
+
+
+class hppa(_RizinBase):
+    arch_cmds = ["e asm.arch=hppa", "e asm.bits=32"]
+
+
+class i4004(_RizinBase):
+    arch_cmds = ["e asm.arch=i4004", "e asm.bits=4"]
+
+
+class i8080(_RizinBase):
+    arch_cmds = ["e asm.arch=i8080", "e asm.bits=8"]
+
+
+class java(_RizinBase):
+    arch_cmds = ["e asm.arch=java", "e asm.bits=32"]
+
+
+class lanai(_RizinBase):
+    arch_cmds = ["e asm.arch=lanai", "e asm.bits=32"]
+
+
+class lh5801(_RizinBase):
+    arch_cmds = ["e asm.arch=lh5801", "e asm.bits=8"]
+
+
+class lm32(_RizinBase):
+    arch_cmds = ["e asm.arch=lm32", "e asm.bits=32"]
+
+
+class luac(_RizinBase):
+    arch_cmds = ["e asm.arch=luac", "e asm.bits=8"]
+
+
+class m68k(_RizinBase):
+    arch_cmds = ["e asm.arch=m68k", "e asm.bits=32"]
+
+
+class m680x_8(_RizinBase):
+    arch_cmds = ["e asm.arch=m680x", "e asm.bits=8"]
+
+
+class m680x_32(_RizinBase):
+    arch_cmds = ["e asm.arch=m680x", "e asm.bits=32"]
+
+
+class malbolge(_RizinBase):
+    arch_cmds = ["e asm.arch=malbolge", "e asm.bits=32"]
+
+
+class mcore(_RizinBase):
+    arch_cmds = ["e asm.arch=mcore", "e asm.bits=32"]
+
+
+class mcs96(_RizinBase):
+    arch_cmds = ["e asm.arch=mcs96", "e asm.bits=16"]
+
+
+class mips_16(_RizinBase):
+    arch_cmds = ["e asm.arch=mips", "e asm.bits=16"]
+
+
+class mips_32(_RizinBase):
+    arch_cmds = ["e asm.arch=mips", "e asm.bits=32"]
+
+
+class mips_64(_RizinBase):
+    arch_cmds = ["e asm.arch=mips", "e asm.bits=64"]
+
+
+class mips_gnu_32(_RizinBase):
+    arch_cmds = ["e asm.arch=mips.gnu", "e asm.bits=32"]
+
+
+class mips_gnu_64(_RizinBase):
+    arch_cmds = ["e asm.arch=mips.gnu", "e asm.bits=64"]
+
+
+class msp430(_RizinBase):
+    arch_cmds = ["e asm.arch=msp430", "e asm.bits=16"]
+
+
+class nios2(_RizinBase):
+    arch_cmds = ["e asm.arch=nios2", "e asm.bits=32"]
+
+
+class or1k(_RizinBase):
+    arch_cmds = ["e asm.arch=or1k", "e asm.bits=32"]
+
+
+class pic(_RizinBase):
+    arch_cmds = ["e asm.arch=pic", "e asm.bits=8"]
+
+
+class ppc_as_32(_RizinBase):
+    arch_cmds = ["e asm.arch=ppc.as", "e asm.bits=32"]
+
+
+class ppc_as_64(_RizinBase):
+    arch_cmds = ["e asm.arch=ppc.as", "e asm.bits=64"]
+
+
+class ppc_32(_RizinBase):
+    arch_cmds = ["e asm.arch=ppc", "e asm.bits=32"]
+
+
+class ppc_64(_RizinBase):
+    arch_cmds = ["e asm.arch=ppc", "e asm.bits=64"]
+
+
+class ppc_gnu_32(_RizinBase):
+    arch_cmds = ["e asm.arch=ppc.gnu", "e asm.bits=32"]
+
+
+class ppc_gnu_64(_RizinBase):
+    arch_cmds = ["e asm.arch=ppc.gnu", "e asm.bits=64"]
+
+
+class propeller(_RizinBase):
+    arch_cmds = ["e asm.arch=propeller", "e asm.bits=32"]
+
+
+class pyc_8(_RizinBase):
+    arch_cmds = ["e asm.arch=pyc", "e asm.bits=8"]
+
+
+class pyc_16(_RizinBase):
+    arch_cmds = ["e asm.arch=pyc", "e asm.bits=16"]
+
+
+class riscv_32(_RizinBase):
+    arch_cmds = ["e asm.arch=riscv", "e asm.bits=32"]
+
+
+class riscv_64(_RizinBase):
+    arch_cmds = ["e asm.arch=riscv", "e asm.bits=64"]
+
+
+class rsp(_RizinBase):
+    arch_cmds = ["e asm.arch=rsp", "e asm.bits=32"]
+
+
+class sh(_RizinBase):
+    arch_cmds = ["e asm.arch=sh", "e asm.bits=32"]
+
+
+class snes_8(_RizinBase):
+    arch_cmds = ["e asm.arch=snes", "e asm.bits=8"]
+
+
+class snes_16(_RizinBase):
+    arch_cmds = ["e asm.arch=snes", "e asm.bits=16"]
+
+
+class sparc_32(_RizinBase):
+    arch_cmds = ["e asm.arch=sparc", "e asm.bits=32"]
+
+
+class sparc_64(_RizinBase):
+    arch_cmds = ["e asm.arch=sparc", "e asm.bits=64"]
+
+
+class sparc_gnu_32(_RizinBase):
+    arch_cmds = ["e asm.arch=sparc.gnu", "e asm.bits=32"]
+
+
+class sparc_gnu_64(_RizinBase):
+    arch_cmds = ["e asm.arch=sparc.gnu", "e asm.bits=64"]
+
+
+class spc700(_RizinBase):
+    arch_cmds = ["e asm.arch=spc700", "e asm.bits=16"]
+
+
+class sysz_32(_RizinBase):
+    arch_cmds = ["e asm.arch=sysz", "e asm.bits=32"]
+
+
+class sysz_64(_RizinBase):
+    arch_cmds = ["e asm.arch=sysz", "e asm.bits=64"]
+
+
+class tms320(_RizinBase):
+    arch_cmds = ["e asm.arch=tms320", "e asm.bits=32"]
+
+
+class tms320c64x(_RizinBase):
+    arch_cmds = ["e asm.arch=tms320c64x", "e asm.bits=32"]
+
+
+class tricore(_RizinBase):
+    arch_cmds = ["e asm.arch=tricore", "e asm.bits=32"]
+
+
+class v810_32(_RizinBase):
+    arch_cmds = ["e asm.arch=v810", "e asm.bits=32"]
+
+
+class v850(_RizinBase):
+    arch_cmds = ["e asm.arch=v850", "e asm.bits=32"]
+
+
+class vax_8(_RizinBase):
+    arch_cmds = ["e asm.arch=vax", "e asm.bits=8"]
+
+
+class vax_32(_RizinBase):
+    arch_cmds = ["e asm.arch=vax", "e asm.bits=32"]
+
+
+class wasm_32(_RizinBase):
+    arch_cmds = ["e asm.arch=wasm", "e asm.bits=32"]
+
+
+class x86_as_16(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.as", "e asm.bits=16"]
+
+
+class x86_as_32(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.as", "e asm.bits=32"]
+
+
+class x86_as_64(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.as", "e asm.bits=64"]
 
 
 class x86_16(_RizinBase):
@@ -217,3 +492,43 @@ class x86_32(_RizinBase):
 
 class x86_64(_RizinBase):
     arch_cmds = ["e asm.arch=x86", "e asm.bits=64"]
+
+
+class x86_nasm_16(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=16"]
+
+
+class x86_nasm_32(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=32"]
+
+
+class x86_nasm_64(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=64"]
+
+
+class x86_nz_16(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=16"]
+
+
+class x86_nz_32(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=32"]
+
+
+class x86_nz_64(_RizinBase):
+    arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=64"]
+
+
+class xap(_RizinBase):
+    arch_cmds = ["e asm.arch=xap", "e asm.bits=16"]
+
+
+class xcore(_RizinBase):
+    arch_cmds = ["e asm.arch=xcore", "e asm.bits=32"]
+
+
+class xtensa(_RizinBase):
+    arch_cmds = ["e asm.arch=xtensa", "e asm.bits=32"]
+
+
+class z80(_RizinBase):
+    arch_cmds = ["e asm.arch=z80", "e asm.bits=8"]
diff --git a/subdisassem/scripts.py b/subdisassem/scripts.py
index 25381aa..3eea0b2 100644
--- a/subdisassem/scripts.py
+++ b/subdisassem/scripts.py
@@ -128,9 +128,92 @@ def subdisassem_script():
         rizin_wrapper.arm_gnu_64,
         rizin_wrapper.arm_wine_16,
         rizin_wrapper.arm_wine_32,
+        rizin_wrapper.avr_8,
+        rizin_wrapper.avr_16,
+        rizin_wrapper.bf_16,
+        rizin_wrapper.bf_32,
+        rizin_wrapper.bf_64,
+        rizin_wrapper.bf_64,
+        rizin_wrapper.chip8,
+        rizin_wrapper.cr_16,
+        rizin_wrapper.cris,
+        rizin_wrapper.dalvik_32,
+        rizin_wrapper.dalvik_64,
+        rizin_wrapper.dcpu16,
+        rizin_wrapper.ebc_32,
+        rizin_wrapper.ebc_64,
+        rizin_wrapper.gb,
+        rizin_wrapper.h8300,
+        rizin_wrapper.hexagon,
+        rizin_wrapper.hppa,
+        rizin_wrapper.i4004,
+        rizin_wrapper.i8080,
+        rizin_wrapper.java,
+        rizin_wrapper.lanai,
+        rizin_wrapper.lh5801,
+        rizin_wrapper.lm32,
+        rizin_wrapper.luac,
+        rizin_wrapper.m68k,
+        rizin_wrapper.m680x_8,
+        rizin_wrapper.m680x_32,
+        rizin_wrapper.malbolge,
+        rizin_wrapper.mcore,
+        rizin_wrapper.mcs96,
+        rizin_wrapper.mips_16,
+        rizin_wrapper.mips_32,
+        rizin_wrapper.mips_64,
+        rizin_wrapper.mips_gnu_32,
+        rizin_wrapper.mips_gnu_64,
+        rizin_wrapper.msp430,
+        rizin_wrapper.nios2,
+        rizin_wrapper.or1k,
+        rizin_wrapper.pic,
+        rizin_wrapper.ppc_as_32,
+        rizin_wrapper.ppc_as_64,
+        rizin_wrapper.ppc_32,
+        rizin_wrapper.ppc_64,
+        rizin_wrapper.ppc_gnu_32,
+        rizin_wrapper.ppc_gnu_64,
+        rizin_wrapper.propeller,
+        rizin_wrapper.pyc_8,
+        rizin_wrapper.pyc_16,
+        rizin_wrapper.riscv_32,
+        rizin_wrapper.riscv_64,
+        rizin_wrapper.rsp,
+        rizin_wrapper.sh,
+        rizin_wrapper.snes_8,
+        rizin_wrapper.snes_16,
+        rizin_wrapper.sparc_32,
+        rizin_wrapper.sparc_64,
+        rizin_wrapper.sparc_gnu_32,
+        rizin_wrapper.sparc_gnu_64,
+        rizin_wrapper.spc700,
+        rizin_wrapper.sysz_32,
+        rizin_wrapper.sysz_64,
+        rizin_wrapper.tms320,
+        rizin_wrapper.tms320c64x,
+        rizin_wrapper.tricore,
+        rizin_wrapper.v810_32,
+        rizin_wrapper.v850,
+        rizin_wrapper.vax_8,
+        rizin_wrapper.vax_32,
+        rizin_wrapper.wasm_32,
+        rizin_wrapper.x86_as_16,
+        rizin_wrapper.x86_as_32,
+        rizin_wrapper.x86_as_64,
         rizin_wrapper.x86_16,
         rizin_wrapper.x86_32,
         rizin_wrapper.x86_64,
+        rizin_wrapper.x86_nasm_16,
+        rizin_wrapper.x86_nasm_32,
+        rizin_wrapper.x86_nasm_64,
+        rizin_wrapper.x86_nz_16,
+        rizin_wrapper.x86_nz_32,
+        rizin_wrapper.x86_nz_64,
+        rizin_wrapper.xap,
+        rizin_wrapper.xcore,
+        rizin_wrapper.xtensa,
+        rizin_wrapper.z80,
     ]
 
     for arch in rizin_archs: