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No commits in common. "d656d97818fdf5a0e92b451410decaa08529f1e9" and "e0c42b84062f4101d527ae15ed4864b2ad7151b2" have entirely different histories.

3 changed files with 28 additions and 575 deletions

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@ -54,72 +54,50 @@ class _CapstoneBase:
def __lt__(self, other):
return len(self) < len(other)
def __contains__(self, name: str):
return hasattr(self, name)
@property
def objdump(self) -> str:
if "_objdump" in self:
return self._objdump
_objdump = str()
opcodes = str()
for opcode in self.disassembly:
_objdump += f"{opcode.address:#02x}:\t{opcode.mnemonic}\t{opcode.op_str}\n"
opcodes += f"{opcode.address:#02x}:\t{opcode.mnemonic}\t{opcode.op_str}\n"
self._objdump = _objdump
return self._objdump
return opcodes
@property
def disasm(self) -> list:
if "_disasm" in self:
return self._disasm
_disasm = list()
opcodes = list()
for opcode in self.disassembly:
if not "unknown" == opcode.mnemonic:
_disasm.append([opcode.address, opcode.mnemonic, opcode.op_str])
opcodes.append([opcode.address, opcode.mnemonic, opcode.op_str])
self._disasm = _disasm
return self._disasm
return opcodes
@property
def rets(self) -> list:
if "_rets" in self:
if hasattr(self, "_rets"):
return self._rets
_rets = list()
self._rets = list()
for opcode in self.disassembly:
if "ret" in opcode.mnemonic:
_rets.append(opcode.mnemonic)
self._rets.append(opcode.mnemonic)
self._rets = _rets
return self._rets
@property
def ret_rates(self) -> list:
if "_ret_rates" in self:
return self._ret_rates
rates = dict()
for mnemonic in set(self.rets):
rates[mnemonic] = self.rets.count(mnemonic)
_ret_rates = sorted(
((value, key) for (key, value) in rates.items()), reverse=True
)
listed = sorted(((value, key) for (key, value) in rates.items()), reverse=True)
self._ret_rates = _ret_rates
return self._ret_rates
return listed
@property
def mnemonic_rates(self) -> list:
if "_mnemonic_rates" in self:
return self._mnemonic_rates
mnemonics = list()
for opcode in self.disassembly:
@ -130,12 +108,9 @@ class _CapstoneBase:
for mnemonic in set(mnemonics):
rates[mnemonic] = mnemonics.count(mnemonic)
_mnemonic_rates = sorted(
((value, key) for (key, value) in rates.items()), reverse=True
)
listed = sorted(((value, key) for (key, value) in rates.items()), reverse=True)
self._mnemonic_rates = _mnemonic_rates
return self._mnemonic_rates
return listed
class x86_16(_CapstoneBase):

View File

@ -20,36 +20,31 @@ class _RizinBase:
return self.objdump
def __len__(self) -> int:
return len(self.disasm)
return len(self.disassembly)
def __lt__(self, other):
return len(self) < len(other)
def __contains__(self, name: str):
return hasattr(self, name)
@property
def objdump(self) -> str:
if "_objdump" in self:
if hasattr(self, "_objdump"):
return self._objdump
_objdump = str()
self._objdump = str()
for each in self.disassembly:
offset = each.get("offset")
opcode = each.get("opcode")
if opcode:
_objdump += f"{offset:#02x}:\t{opcode}\n"
self._objdump += f"{offset:#02x}:\t{opcode}\n"
self._objdump = _objdump
return self._objdump
@property
def disasm(self) -> list:
if "_disasm" in self:
if hasattr(self, "_disasm"):
return self._disasm
_disasm = list()
self._disasm = list()
for each in self.disassembly:
offset = each.get("offset")
@ -58,32 +53,30 @@ class _RizinBase:
if opcode:
mnemonic = opcode.split(" ")[0]
opcode = opcode.split(" ")[1:]
_disasm.append([offset, mnemonic, opcode])
else:
mnemonic = None
self._disasm.append([offset, mnemonic, opcode])
self._disasm = _disasm
return self._disasm
@property
def rets(self) -> list:
if "_rets" in self:
if hasattr(self, "_rets"):
return self._rets
_rets = list()
self._rets = list()
for each in self.disasm:
_, mnemonic, _ = each
if mnemonic and "ret" in mnemonic:
_rets.append(mnemonic)
self._rets.append(mnemonic)
self._rets = _rets
return self._rets
@property
def ret_rates(self) -> list:
if "_ret_rates" in self:
return self._ret_rates
rates = dict()
for mnemonic in set(self.rets):
@ -93,14 +86,10 @@ class _RizinBase:
((value, key) for (key, value) in rates.items()), reverse=True
)
self._ret_rates = _ret_rates
return self._ret_rates
return _ret_rates
@property
def mnemonic_rates(self) -> list:
if "_mnemonic_rates" in self:
return self._mnemonic_rates
mnemonics = list()
for each in self.disasm:
@ -118,417 +107,8 @@ class _RizinBase:
((value, key) for (key, value) in rates.items()), reverse=True
)
self._mnemonic_rates = _mnemonic_rates
return self._mnemonic_rates
class _6502_8(_RizinBase):
arch_cmds = ["e asm.arch=6502", "e asm.bits=8"]
class _6502_16(_RizinBase):
arch_cmds = ["e asm.arch=6502", "e asm.bits=16"]
class _8051(_RizinBase):
arch_cmds = ["e asm.arch=8051", "e asm.bits=8"]
class amd29k(_RizinBase):
arch_cmds = ["e asm.arch=amd29k", "e asm.bits=32"]
class arc_16(_RizinBase):
arch_cmds = ["e asm.arch=arc", "e asm.bits=16"]
class arc_32(_RizinBase):
arch_cmds = ["e asm.arch=arc", "e asm.bits=32"]
class arm_as_16(_RizinBase):
arch_cmds = ["e asm.arch=arm.as", "e asm.bits=16"]
class arm_as_32(_RizinBase):
arch_cmds = ["e asm.arch=arm.as", "e asm.bits=32"]
class arm_as_64(_RizinBase):
arch_cmds = ["e asm.arch=arm.as", "e asm.bits=64"]
class arm_16(_RizinBase):
arch_cmds = ["e asm.arch=arm", "e asm.bits=16"]
class arm_32(_RizinBase):
arch_cmds = ["e asm.arch=arm", "e asm.bits=32"]
class arm_64(_RizinBase):
arch_cmds = ["e asm.arch=arm", "e asm.bits=64"]
class arm_gnu_16(_RizinBase):
arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=16"]
class arm_gnu_32(_RizinBase):
arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=32"]
class arm_gnu_64(_RizinBase):
arch_cmds = ["e asm.arch=arm.gnu", "e asm.bits=64"]
class arm_wine_16(_RizinBase):
arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=16"]
class arm_wine_32(_RizinBase):
arch_cmds = ["e asm.arch=arm.winedbg", "e asm.bits=32"]
class avr_8(_RizinBase):
arch_cmds = ["e asm.arch=avr", "e asm.bits=8"]
class avr_16(_RizinBase):
arch_cmds = ["e asm.arch=avr", "e asm.bits=16"]
class bf_16(_RizinBase):
arch_cmds = ["e asm.arch=bf", "e asm.bits=16"]
class bf_32(_RizinBase):
arch_cmds = ["e asm.arch=bf", "e asm.bits=32"]
class bf_64(_RizinBase):
arch_cmds = ["e asm.arch=bf", "e asm.bits=64"]
class bf_64(_RizinBase):
arch_cmds = ["e asm.arch=bf", "e asm.bits=64"]
class chip8(_RizinBase):
arch_cmds = ["e asm.arch=chip8", "e asm.bits=32"]
class cr_16(_RizinBase):
arch_cmds = ["e asm.arch=cr16", "e asm.bits=16"]
class cris(_RizinBase):
arch_cmds = ["e asm.arch=cris", "e asm.bits=32"]
class dalvik_32(_RizinBase):
arch_cmds = ["e asm.arch=dalvik", "e asm.bits=32"]
class dalvik_64(_RizinBase):
arch_cmds = ["e asm.arch=dalvik", "e asm.bits=64"]
class dcpu16(_RizinBase):
arch_cmds = ["e asm.arch=dcpu16", "e asm.bits=16"]
class ebc_32(_RizinBase):
arch_cmds = ["e asm.arch=ebc", "e asm.bits=32"]
class ebc_64(_RizinBase):
arch_cmds = ["e asm.arch=ebc", "e asm.bits=64"]
class gb(_RizinBase):
arch_cmds = ["e asm.arch=gb", "e asm.bits=16"]
class h8300(_RizinBase):
arch_cmds = ["e asm.arch=h8300", "e asm.bits=16"]
class hexagon(_RizinBase):
arch_cmds = ["e asm.arch=hexagon", "e asm.bits=32"]
class hppa(_RizinBase):
arch_cmds = ["e asm.arch=hppa", "e asm.bits=32"]
class i4004(_RizinBase):
arch_cmds = ["e asm.arch=i4004", "e asm.bits=4"]
class i8080(_RizinBase):
arch_cmds = ["e asm.arch=i8080", "e asm.bits=8"]
class java(_RizinBase):
arch_cmds = ["e asm.arch=java", "e asm.bits=32"]
class lanai(_RizinBase):
arch_cmds = ["e asm.arch=lanai", "e asm.bits=32"]
class lh5801(_RizinBase):
arch_cmds = ["e asm.arch=lh5801", "e asm.bits=8"]
class lm32(_RizinBase):
arch_cmds = ["e asm.arch=lm32", "e asm.bits=32"]
class luac(_RizinBase):
arch_cmds = ["e asm.arch=luac", "e asm.bits=8"]
class m68k(_RizinBase):
arch_cmds = ["e asm.arch=m68k", "e asm.bits=32"]
class m680x_8(_RizinBase):
arch_cmds = ["e asm.arch=m680x", "e asm.bits=8"]
class m680x_32(_RizinBase):
arch_cmds = ["e asm.arch=m680x", "e asm.bits=32"]
class malbolge(_RizinBase):
arch_cmds = ["e asm.arch=malbolge", "e asm.bits=32"]
class mcore(_RizinBase):
arch_cmds = ["e asm.arch=mcore", "e asm.bits=32"]
class mcs96(_RizinBase):
arch_cmds = ["e asm.arch=mcs96", "e asm.bits=16"]
class mips_16(_RizinBase):
arch_cmds = ["e asm.arch=mips", "e asm.bits=16"]
class mips_32(_RizinBase):
arch_cmds = ["e asm.arch=mips", "e asm.bits=32"]
class mips_64(_RizinBase):
arch_cmds = ["e asm.arch=mips", "e asm.bits=64"]
class mips_gnu_32(_RizinBase):
arch_cmds = ["e asm.arch=mips.gnu", "e asm.bits=32"]
class mips_gnu_64(_RizinBase):
arch_cmds = ["e asm.arch=mips.gnu", "e asm.bits=64"]
class msp430(_RizinBase):
arch_cmds = ["e asm.arch=msp430", "e asm.bits=16"]
class nios2(_RizinBase):
arch_cmds = ["e asm.arch=nios2", "e asm.bits=32"]
class or1k(_RizinBase):
arch_cmds = ["e asm.arch=or1k", "e asm.bits=32"]
class pic(_RizinBase):
arch_cmds = ["e asm.arch=pic", "e asm.bits=8"]
class ppc_as_32(_RizinBase):
arch_cmds = ["e asm.arch=ppc.as", "e asm.bits=32"]
class ppc_as_64(_RizinBase):
arch_cmds = ["e asm.arch=ppc.as", "e asm.bits=64"]
class ppc_32(_RizinBase):
arch_cmds = ["e asm.arch=ppc", "e asm.bits=32"]
class ppc_64(_RizinBase):
arch_cmds = ["e asm.arch=ppc", "e asm.bits=64"]
class ppc_gnu_32(_RizinBase):
arch_cmds = ["e asm.arch=ppc.gnu", "e asm.bits=32"]
class ppc_gnu_64(_RizinBase):
arch_cmds = ["e asm.arch=ppc.gnu", "e asm.bits=64"]
class propeller(_RizinBase):
arch_cmds = ["e asm.arch=propeller", "e asm.bits=32"]
class pyc_8(_RizinBase):
arch_cmds = ["e asm.arch=pyc", "e asm.bits=8"]
class pyc_16(_RizinBase):
arch_cmds = ["e asm.arch=pyc", "e asm.bits=16"]
class riscv_32(_RizinBase):
arch_cmds = ["e asm.arch=riscv", "e asm.bits=32"]
class riscv_64(_RizinBase):
arch_cmds = ["e asm.arch=riscv", "e asm.bits=64"]
class rsp(_RizinBase):
arch_cmds = ["e asm.arch=rsp", "e asm.bits=32"]
class sh(_RizinBase):
arch_cmds = ["e asm.arch=sh", "e asm.bits=32"]
class snes_8(_RizinBase):
arch_cmds = ["e asm.arch=snes", "e asm.bits=8"]
class snes_16(_RizinBase):
arch_cmds = ["e asm.arch=snes", "e asm.bits=16"]
class sparc_32(_RizinBase):
arch_cmds = ["e asm.arch=sparc", "e asm.bits=32"]
class sparc_64(_RizinBase):
arch_cmds = ["e asm.arch=sparc", "e asm.bits=64"]
class sparc_gnu_32(_RizinBase):
arch_cmds = ["e asm.arch=sparc.gnu", "e asm.bits=32"]
class sparc_gnu_64(_RizinBase):
arch_cmds = ["e asm.arch=sparc.gnu", "e asm.bits=64"]
class spc700(_RizinBase):
arch_cmds = ["e asm.arch=spc700", "e asm.bits=16"]
class sysz_32(_RizinBase):
arch_cmds = ["e asm.arch=sysz", "e asm.bits=32"]
class sysz_64(_RizinBase):
arch_cmds = ["e asm.arch=sysz", "e asm.bits=64"]
class tms320(_RizinBase):
arch_cmds = ["e asm.arch=tms320", "e asm.bits=32"]
class tms320c64x(_RizinBase):
arch_cmds = ["e asm.arch=tms320c64x", "e asm.bits=32"]
class tricore(_RizinBase):
arch_cmds = ["e asm.arch=tricore", "e asm.bits=32"]
class v810_32(_RizinBase):
arch_cmds = ["e asm.arch=v810", "e asm.bits=32"]
class v850(_RizinBase):
arch_cmds = ["e asm.arch=v850", "e asm.bits=32"]
class vax_8(_RizinBase):
arch_cmds = ["e asm.arch=vax", "e asm.bits=8"]
class vax_32(_RizinBase):
arch_cmds = ["e asm.arch=vax", "e asm.bits=32"]
class wasm_32(_RizinBase):
arch_cmds = ["e asm.arch=wasm", "e asm.bits=32"]
class x86_as_16(_RizinBase):
arch_cmds = ["e asm.arch=x86.as", "e asm.bits=16"]
class x86_as_32(_RizinBase):
arch_cmds = ["e asm.arch=x86.as", "e asm.bits=32"]
class x86_as_64(_RizinBase):
arch_cmds = ["e asm.arch=x86.as", "e asm.bits=64"]
return _mnemonic_rates
class x86_16(_RizinBase):
arch_cmds = ["e asm.arch=x86", "e asm.bits=16"]
class x86_32(_RizinBase):
arch_cmds = ["e asm.arch=x86", "e asm.bits=32"]
class x86_64(_RizinBase):
arch_cmds = ["e asm.arch=x86", "e asm.bits=64"]
class x86_nasm_16(_RizinBase):
arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=16"]
class x86_nasm_32(_RizinBase):
arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=32"]
class x86_nasm_64(_RizinBase):
arch_cmds = ["e asm.arch=x86.nasm", "e asm.bits=64"]
class x86_nz_16(_RizinBase):
arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=16"]
class x86_nz_32(_RizinBase):
arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=32"]
class x86_nz_64(_RizinBase):
arch_cmds = ["e asm.arch=x86.nz", "e asm.bits=64"]
class xap(_RizinBase):
arch_cmds = ["e asm.arch=xap", "e asm.bits=16"]
class xcore(_RizinBase):
arch_cmds = ["e asm.arch=xcore", "e asm.bits=32"]
class xtensa(_RizinBase):
arch_cmds = ["e asm.arch=xtensa", "e asm.bits=32"]
class z80(_RizinBase):
arch_cmds = ["e asm.arch=z80", "e asm.bits=8"]

View File

@ -111,109 +111,7 @@ def subdisassem_script():
session.commit()
rizin_archs = [
rizin_wrapper._6502_8,
rizin_wrapper._6502_16,
rizin_wrapper._8051,
rizin_wrapper.amd29k,
rizin_wrapper.arc_16,
rizin_wrapper.arc_32,
rizin_wrapper.arm_as_16,
rizin_wrapper.arm_as_32,
rizin_wrapper.arm_as_64,
rizin_wrapper.arm_16,
rizin_wrapper.arm_32,
rizin_wrapper.arm_64,
rizin_wrapper.arm_gnu_16,
rizin_wrapper.arm_gnu_32,
rizin_wrapper.arm_gnu_64,
rizin_wrapper.arm_wine_16,
rizin_wrapper.arm_wine_32,
rizin_wrapper.avr_8,
rizin_wrapper.avr_16,
rizin_wrapper.bf_16,
rizin_wrapper.bf_32,
rizin_wrapper.bf_64,
rizin_wrapper.bf_64,
rizin_wrapper.chip8,
rizin_wrapper.cr_16,
rizin_wrapper.cris,
rizin_wrapper.dalvik_32,
rizin_wrapper.dalvik_64,
rizin_wrapper.dcpu16,
rizin_wrapper.ebc_32,
rizin_wrapper.ebc_64,
rizin_wrapper.gb,
rizin_wrapper.h8300,
rizin_wrapper.hexagon,
rizin_wrapper.hppa,
rizin_wrapper.i4004,
rizin_wrapper.i8080,
rizin_wrapper.java,
rizin_wrapper.lanai,
rizin_wrapper.lh5801,
rizin_wrapper.lm32,
rizin_wrapper.luac,
rizin_wrapper.m68k,
rizin_wrapper.m680x_8,
rizin_wrapper.m680x_32,
rizin_wrapper.malbolge,
rizin_wrapper.mcore,
rizin_wrapper.mcs96,
rizin_wrapper.mips_16,
rizin_wrapper.mips_32,
rizin_wrapper.mips_64,
rizin_wrapper.mips_gnu_32,
rizin_wrapper.mips_gnu_64,
rizin_wrapper.msp430,
rizin_wrapper.nios2,
rizin_wrapper.or1k,
rizin_wrapper.pic,
rizin_wrapper.ppc_as_32,
rizin_wrapper.ppc_as_64,
rizin_wrapper.ppc_32,
rizin_wrapper.ppc_64,
rizin_wrapper.ppc_gnu_32,
rizin_wrapper.ppc_gnu_64,
rizin_wrapper.propeller,
rizin_wrapper.pyc_8,
rizin_wrapper.pyc_16,
rizin_wrapper.riscv_32,
rizin_wrapper.riscv_64,
rizin_wrapper.rsp,
rizin_wrapper.sh,
rizin_wrapper.snes_8,
rizin_wrapper.snes_16,
rizin_wrapper.sparc_32,
rizin_wrapper.sparc_64,
rizin_wrapper.sparc_gnu_32,
rizin_wrapper.sparc_gnu_64,
rizin_wrapper.spc700,
rizin_wrapper.sysz_32,
rizin_wrapper.sysz_64,
rizin_wrapper.tms320,
rizin_wrapper.tms320c64x,
rizin_wrapper.tricore,
rizin_wrapper.v810_32,
rizin_wrapper.v850,
rizin_wrapper.vax_8,
rizin_wrapper.vax_32,
rizin_wrapper.wasm_32,
rizin_wrapper.x86_as_16,
rizin_wrapper.x86_as_32,
rizin_wrapper.x86_as_64,
rizin_wrapper.x86_16,
rizin_wrapper.x86_32,
rizin_wrapper.x86_64,
rizin_wrapper.x86_nasm_16,
rizin_wrapper.x86_nasm_32,
rizin_wrapper.x86_nasm_64,
rizin_wrapper.x86_nz_16,
rizin_wrapper.x86_nz_32,
rizin_wrapper.x86_nz_64,
rizin_wrapper.xap,
rizin_wrapper.xcore,
rizin_wrapper.xtensa,
rizin_wrapper.z80,
]
for arch in rizin_archs: